1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, relates to a semiconductor memory device having a write protect function in which both ROM areas and RAM areas are mixed on the same chip.
2. Description of the Related Art
Since a nonvolatile read write memory (RWM) retains data written thereon even after it is disconnected from a power supply, part of a memory area thereof can be used as a read only memory (ROM). ROM stores data to be protected from being erased (hereinafter referred to as ROM data). When the non-volatile RWM is used for this purpose, however, it is necessary to ensure that after the ROM data has been stored in the memory area no additional data should be written over the ROM data.
Conventionally, whether writing is permitted or inhibited for a specific memory area has been controlled by an external program through a CPU. In such an external control, in case that the program should have a bug or that a noise should arise during the control, a runaway or a malfunction of the CPU may be caused. As a result, new data may be written over ROM data stored in the memory area of the non-volatile RWM used in place of a ROM and thus the ROM data may be erased.
Japanese Laid-Open Patent Publication No. 3-129446 discloses a computer incorporating an EEPROM (electrically erasable/programmable read-only memory). This computer includes an area designating means (a write area register) for generating a signal designating areas on the EEPROM as write permissible or write protected. The computer also includes a means for comparing the area designated as write permissible by the area designating means with an area designated by data supplied from an address bus, so as to inhibit the data from being written on the area of the EEPROM when the two areas are not identical.
In the above computer, however, it is necessary to supply an address space identification signal which is produced by decoding data from an address decoder to the comparing means. Another address decoder is therefore required in addition to the address decoder for the EEPROM.
Japanese Laid-Open Patent Publication No. 2-2435 discloses a nonvolatile semiconductor memory device which includes a rewrite inhibit circuit for inhibiting rewriting on some memory cells. According to the rewrite inhibit circuit, a high voltage required for rewriting is not applied to such memory cells. The operation of the rewrite inhibit circuit is controlled in accordance with the potential of an input thereto from outside.
In the above semiconductor memory device, however, since the operation of the rewrite inhibit circuit is controlled in accordance with the potential of an input thereto from outside, it is necessary to provide an outer circuit for determining whether writing for a specific address is permissible or not.
Japanese Laid-Open Patent Publication No. 62-202395 discloses a semiconductor integrated circuit device having an input terminal for receiving a write protect signal. The device includes a decoder which does not output a row selective signal for a specific address designation input thereto when the write protect signal is being input from the input terminal.
However, in the above semiconductor integrated circuit device, when writing is inhibited for one of the bit lines selected at a certain cycle, reading from the bit line is not possible, either.
Japanese Laid-Open Patent Publication No. 61-271687 discloses a magnetic bubble cassette having a plurality of memory blocks. The cassette includes a means for generating a write permit signal or a write inhibit signal for each memory block, and a means for detecting the write inhibit signal when a write instruction is supplied. Writing is not performed when the write inhibit signal is detected. The write permit or write inhibit is designated by switching.
In the above magnetic bubble cassette, however, since the write permit or the write inhibit is designated for each memory block, it is not possible to define a smaller area for the write inhibit area.